European Patent Application EP-A-190508 describes a method of manufacturing a static induction transistor, which method comprises providing first and second semiconductor bodies each having first and second major surfaces, defining a rectifying junction pattern adjacent to at least one of the first major surfaces, and bonding the first major surfaces together to join the two semiconductor bodies to form the semiconductor device in which the rectifying junction pattern defines a path for the flow of charge carriers between the second major surfaces.
As described with reference to FIGS. 4A to 4F of EP-A-190508, the two first major surfaces are bonded by a process known as `slice-bonding` or `slice-wringing` in which the first major surfaces are polished so as to be optically flat with a surface roughness of less than 50 nm (nanometers) and preferably less than 5 nm, this process being known as `mirror-polishing`. The mirror-polished first major surfaces are brought into contact to establish bonding between the first major surfaces, and the joined bodies then subjected to a heat treatment to strengthen the bond.
Prior to bringing the first major surfaces into contact, the rectifying junction pattern is defined by introducing ions of the opposite conductivity type to the first and second semiconductor bodies into the one first major surface through an appropriate mask to define a layer pattern of the opposite conductivity type which, after bonding of the first and second semiconductor bodies, forms a pn junction with the first and second semiconductor bodies which defines the path for the flow of charge carriers between the second major surfaces and provides a buried gate layer of the static induction transistor. Electrical contact is made to the buried gate layer to enable a bias voltage to be applied to control the charge carrier path by etching a groove through one of the first and second semiconductor bodies to define a mesa structure exposing part of the gate transistor. Electrical contacts are also provided on the two second major surfaces to complete the device.